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Sunday, 28 October 2018

We are currently hiring VLSI Engineers - Physical Design, Physical Verification, STA/ Synthesis design, SoC/IP Verification, RTL Design, Lint, CDC, Spyglass, Analog Circuit design, DFT Design, Post silicon validation

Experience level – 2 to 12 Years.
Location – Bangalore / Vizag / Kochi / Malaysia / USA. Physical Design Physical Verification STA/ Synthesis design SoC/IP Verification RTL Design, Lint, CDC, Spyglass Analog Circuit design DFT Design Post silicon validation Interested Candidates Share your Updated resume at pragathi.chighulapally@cerium-systems.com
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